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2.6.3 A Simple Example
How do we make and
use datapath elements? What does a design look like? We may use predesigned
cells from a library or build the elements ourselves from logic cells using
a schematic or a design language. Table 2.12 shows an 8-bit conditional-sum
adder intended for an FPGA. This Verilog implementation uses the same structure
as Figure 2.25, but the equations are collapsed to use four or five
variables. A basic logic cell in certain Xilinx FPGAs, for example, can
implement two equations of the same four variables or one equation with
five variables. The equations shown in Table 2.12 requires three levels
of FPGA logic cells (so, for example, if each FPGA logic cell has a 5 ns
delay, the 8-bit conditional-sum adder delay is 15 ns).
TABLE 2.12 An
8-bit conditional-sum adder (the notation is described in Figure 2.25). |
| module
m8bitCSum (C0, a, b, s, C8); // Verilog conditional-sum adder for an FPGA
input [7:0]
C0, a, b; output [7:0] s; output C8;
wire A7,A6,A5,A4,A3,A2,A1,A0,B7,B6,B5,B4,B3,B2,B1,B0,S8,S7,S6,S5,S4,S3,S2,S1,S0;
wire C0,
C2, C4_2_0, C4_2_1, S5_4_0, S5_4_1, C6, C6_4_0, C6_4_1, C8;
assign {A7,A6,A5,A4,A3,A2,A1,A0} = a;
assign {B7,B6,B5,B4,B3,B2,B1,B0} = b;
assign s = { S7,S6,S5,S4,S3,S2,S1,S0 };
assign S0
= A0^B0^C0 ; // start of level 1: & = AND, ^ = XOR, | = OR, ! = NOT
assign S1
= A1^B1^(A0&B0|(A0|B0)&C0) ;
assign C2 = A1&B1|(A1|B1)&(A0&B0|(A0|B0)&C0)
; assign
C4_2_0 = A3&B3|(A3|B3)&(A2&B2) ; assign C4_2_1 = A3&B3|(A3|B3)&(A2|B2)
; assign
S5_4_0 = A5^B5^(A4&B4) ; assign S5_4_1 = A5^B5^(A4|B4) ;
assign C6_4_0
= A5&B5|(A5|B5)&(A4&B4) ; assign C6_4_1 = A5&B5|(A5|B5)&(A4|B4)
; assign
S2 = A2^B2^C2 ; // start of level 2
assign S3 = A3^B3^(A2&B2|(A2|B2)&C2)
; assign
S4 = A4^B4^(C4_2_0|C4_2_1&C2) ;
assign S5 = S5_4_0& !(C4_2_0|C4_2_1&C2)|S5_4_1&(C4_2_0|C4_2_1&C2)
; assign
C6 = C6_4_0|C6_4_1&(C4_2_0|C4_2_1&C2) ;
assign S6 = A6^B6^C6 ; // start of level
3 assign
S7 = A7^B7^(A6&B6|(A6|B6)&C6) ;
assign C8 = A7&B7|(A7|B7s)&(A6&B6|(A6|B6)&C6)
; endmodule
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Figure 2.26 shows the normalized
delay and area figures for a set of predesigned datapath adders. The data
in Figure 2.26 is from a series of ASIC datapath cell libraries (Compass
Passport) that may be synthesized together with test vectors and simulation
models. We can combine the different adder techniques, but the adders then
lose regularity and become less suited to a datapath implementation.
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FIGURE 2.26 Datapath
adders. This data is from a series of submicron datapath libraries. (a) Delay
normalized to a two-input NAND logic cell delay (approximately equal to
250 ps in a 0.5
m m process). For example, a 64-bit ripple-carry adder (RCA) has
a delay of approximately 30 ns
in a 0.5 m m process.
The spread in delay is due to variation in delays between different inputs
and outputs. An n -bit RCA has a
delay proportional to n . The delay
of an n -bit carry-select adder
is approximately proportional to log
2
n . The carry-save adder delay is constant (but requires a carry-propagate
adder to complete an addition). (b) In a datapath library the area
of all adders are proportional to the bit size. |
There are other adders that are
not used in datapaths, but are occasionally useful in ASIC design. A serial
adder is smaller but slower than the parallel adders we have
described [Denyer and Renshaw, 1985]. The carry-completion adder
is a variable delay adder and rarely used in synchronous designs [Sklansky,
1960].
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