RISC-V Foundation Announces Agenda for RISC-V Workshop Zurich

Wednesday, June 12, 2019:

  • RISC-V Software State of the Union
    • When: 9:25 – 09:50 CEST
    • Who: Palmer Dabbelt, SiFive
  • Open Source Compiler Tool Chains for RISC-V
    • When: 9:50 – 10:15 CEST
    • Who: Jeremy Bennett, Embecosm
  • Enabling RISC-V Development with QEMU
    • When: 10:15 – 10:30 CEST
    • Who: Alistair Francis, Western Digital
  • Building Better Soft RISC-V IP Cores through Mi-V Verification and Compliance Testing
    • When: 11:00 – 11:25 CEST
    • Who: Stuart Hoad, Microchip Technology
  • Embench TM: A Free Benchmark Suite for Embedded Computing from an Academic-Industry Cooperative (Towards the Long Overdue and Deserved Demise of Dhrystone)
    • When: 11:25 – 11:50 CEST
    • Who: David Patterson, RISC-V Foundation; Jeremy Bennett, Embecosm
  • Developing with FreeRTOS and RISC-V
    • When: 11:50 – 12:15 CEST
    • Who: Richard Barry, AWS
  • Enable RISC-V Capability in Cloud Computing
    • When: 12:15 – 12:30 CEST
    • Who: Zhipeng Huang, Huawei
  • SweRV (RISC-V) Debug, Trace and On-Chip Analytics for SOC
    • When: 13:30 – 13:45 CEST
    • Who: Sesibhushana Rao Bommana and Mukesh Panda, Western Digital
  • TestRIG: Using RVFI-DII to Eliminate the "Test Gap" Between Specification and Implementation
    • When: 13:45 – 14:00 CEST
    • Who: Jonathan Woodruff, University of Cambridge
  • Formal Verification of PULPino and Other RISC-V SoCs
    • When: 14:00 – 14:15 CEST
    • Who: Nicolae Tusinchi and Sven Beyer, OneSpin Solutions
  • Ada & PolarFire SoC, a Software and Hardware Alloy for Safety & Security
    • When: 14:15 – 14:30 CEST
    • Who: Fabien Chouteau, AdaCore; Pierre Selwan, Microsemi, a Microchip company
  • Building Secure Systems using RISC-V and Rust
    • When: 14:30 – 14:45 CEST
    • Who: Arun Thomas, Draper Labs
  • 60 Second Poster Preview Sessions
    • When: 14:45 – 15:15 CEST
  • An Open-Source API Proposal for a Multi-Domain RISC-V Trusted Execution Environment
    • When: 15:45 – 16:10 CEST
    • Who: Cesare Garlati, Hex Five Security
  • Protecting RISC-V Processors Against Physical Attacks
    • When: 16:10 – 16:25 CEST
    • Who: Mario Werner, Graz University of Technology
  • A Security Policy Definition Language, Semantics, and Open Source Tools
    • When: 16:25 – 16:40 CEST
    • Who: Greg Sullivan, Dover Microsystems; Chris Casinghino, Draper Labs
  • An Intrinsically Secure RISC V processor
    • When: 16:40 – 16:55 CEST
    • Who: Olivier Savry, CEA
  • SiFive 7-Series RISC-V Core IP Enables Embedded Intelligence
    • When: 16:55 – 17:10 CEST
    • Who: Yunsup Lee, SiFive
  • CloudBEAR RISC-V Processor IP Product Line
    • When: 17:10 – 17:25 CEST
    • Who: Alexander Kozlov, CloudBEAR
  • Syntacore 64bit RISC-V Core IP Product Line
    • When: 17:25 – 17:40 CEST
    • Who: Alexander Redkin and Dmitry Gusev, Syntacore
  • Configurable LLDB Debuggers for RISC-V
    • When: 17:40 – 17:55 CEST
    • Who: To be announced

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