⁴ Testing performed by AMD Engineering as of October 2018 using AMD reference system with a pre-production “Rome” engineering sample, where “Rome” scored approximately 2x higher compared to “Naples” System.

⁵ Estimated generational increase based upon AMD internal design specifications for “Zen 2” compared to “Zen 1”.  “Zen 2” has 2X the core density of “Zen 1”, and when multiplied by 2X peak FLOPs per core, at the same frequency, results in 4X the FLOPs in throughput.

⁶ Estimates based on AMD internal testing as of November 6, 2018 in AMD “Ethanol” reference system (Oct 2018?) AMD EPYC™-based system configuration with AMD “Rome” Development Chassis with  an EthanolX development board featuring a single next generation AMD EPYC (“Rome”) processor with a total of XXXXX DIMMs at XXXXX; versus Intel -based system configured with Supermicro’s SYS-1029U-TRTP; OS: Ubuntu 7.3.0-27ubuntu1~18.04; Linux: 4.15.0-36-generic; Compiler: GCC 7.3.0 with 2x Intel(R) Xeon(R) Platinum 8180M CPU, 24x32GB at 2666 MHz. The AMD “Rome” 1P server completes the C-Ray demo in ~ XXXXX sec and the Intel 8180M completes the benchmark in ~ XXXXX sec.  Benchmark testing data redacted by AMD for confidentiality purposes, full disclosure will be available after launch.  

⁷ As of Oct 22, 2018. The results calculated on for Radeon Instinct MI60 designed with Vega 7nm FinFET process technology resulted in 29.5 TFLOPS half precision (FP16), 14.8 TFLOPS single precision (FP32) and 7.4 TFLOPS double precision (FP64) peak theoretical floating-point performance. This performance increase is achieved with an improved transistor count of 13.2 billion on a smaller die size of 331.46mm² then previous Gen MI25 GPU products with the same 300W power envelope.

The results calculated for Radeon Instinct MI50 designed with Vega 7nm FinFET process technology resulted in 26.8 TFLOPS peak half precision (FP16), 13.4 TFLOPS peak single precision (FP32) and 6.7 TFLOPS peak double precision (FP64) floating-point performance. This performance increase is achieved with an improved transistor count of 13.2 billion on a smaller die size of 331.46mm² than previous Gen MI25 GPU products with the same 300W power envelope.

The results calculated for Radeon Instinct MI25 GPU based on the “Vega10” architecture resulted in 24.6 TFLOPS peak half precision (FP16), 12.3 TFLOPS peak single precision (FP32) and 768 GFLOPS peak double precision (FP64) floating-point performance. This performance is achieved with a transistor count of 12.5 billion on a die size of 494.8mm² with 300W power envelope.

AMD TFLOPS calculations conducted with the following equation for Radeon Instinct MI25, MI50, and MI60 GPUs: FLOPS calculations are performed by taking the engine clock from the highest DPM state and multiplying it by xx CUs per GPU. Then, multiplying that number by xx stream processors, which exist in each CU. Then, that number is multiplied by 2 FLOPS per clock for FP32 and 4 FLOPS per clock for FP16. To calculate FP64 TFLOPS rate for Vega 7nm products MI50 and MI60 a 1/2 rate is used and for “Vega10” architecture based MI25 a 1/16^th rate is used.

TFLOP calculations for MI50 and MI60 GPUs can be found at https://www.amd.com/en/products/professional-graphics/instinct-mi50 and https://www.amd.com/en/products/professional-graphics/instinct-mi60

Industry supporting documents / web pages:
http://www.tsmc.com/english/dedicatedFoundry/technology/7nm.htm
https://www.globalfoundries.com/sites/default/files/product-briefs/product-brief-7lp-7nm-finfet-technology.pdf

AMD has not independently tested or verified external/third party results/data and bears no responsibility for any errors or omissions therein.
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⁸ Radeon Instinct™ MI60 contains 13.2 billion transistors on a package size of 331.46mm2, while the previous generation Radeon Instinct™ MI25 had 12.5 billion transistors on a package size of 494.8mm2 – a 58% improvement in number of transistors per mm2.

Contact:
Sarah Youngbauer
 AMD Communications
(512) 602-3028
Email Contact

Laura Graves
AMD Investor Relations
(408) 749-5467
Email Contact

A photo accompanying this announcement is available at http://www.globenewswire.com/NewsRoom/AttachmentNg/4568eb33-da69-4f44-8b61-5aafbb71788c