The RISC-V Summit to Host Multi-Track Technical Sessions, an Exhibition Hall and Keynotes from Antmicro, Facebook, Microchip, NXP, SiFive and Western Digital

BERKELEY, Calif. — (BUSINESS WIRE) — October 1, 2018 — The RISC-V Foundation, a nonprofit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), today announced the agenda for its first annual RISC-V Summit at the Santa Clara Convention Center in Santa Clara, Calif., taking place Dec. 3-6, 2018. The Summit, in partnership with Informa’s Knowledge & Networking Division, KNect365, will gather the RISC-V ecosystem for a multi-track technical conference featuring keynotes, tutorials, exhibitions and networking receptions.

Keynotes will feature speakers from Antmicro, Facebook, Microchip, NXP, SiFive, Western Digital and more:

Tuesday, Dec. 4, 2018:

• RISC-V State of the Union
  • When: 8:50 a.m. – 9:20 a.m. PST
  • Who: Krste Asanovic, Co-Founder & Chief Architect, SiFive and Chairman of the Board, RISC-V Foundation
• Unleashing Innovation From Core to Edge
  • When: 9:20 a.m. – 9:40 a.m. PST
  • Who: Martin Fink, Executive Vice President and Chief Technology Officer of Western Digital
• Enabling the Freedom to Innovate
  • When: 9:40 a.m. – 10 a.m. PST
  • Who: Patrick Johnson, Vice President, Mixed Signal and FPGA Business Units of Microchip
• The 100X Problem – How to Redefine Silicon for Augmented Reality
  • When: 11:20 a.m. – 11:40 a.m. PST
  • Who: Robert Shearer, Director of Silicon Architecture and Modeling of Facebook

Wednesday, Dec. 5, 2018:

• A New Golden Age for Computer Architecture: History, Challenges and Opportunities
  • When: 8:30 a.m. – 9 a.m. PST
  • Who: David Patterson, Vice Chairman, Board of Directors, RISC-V Foundation

• Opportunities and Challenges of Building Silicon in the Cloud
  • When: 9 a.m. – 9:20 a.m. PST
  • Who: Yunsup Lee, Chief Technology Officer of SiFive and Chairman of the Technical Task Group, RISC-V Foundation
• Deepening the RISC-V Ecosystem to Drive Industry-Wide Adoption
  • When : 9:20 a.m. – 9:40 a.m. PST
  • Who : Rob Oshana, Vice President, Software Engineering of NXP and Board Member, RISC-V Foundation
• Accelerating Innovation: Why Google's TPU Was Just the Start
  • When : 9:40 a.m. – 10 a.m. PST
  • Who : Michael Gielda, Vice President Business Development of Antmicro
  The technical tracks, presented by members of the RISC-V community, will focus on Open RISC-V Platforms, RISC-V Accelerators and Security in RISC-V. For more information on each presentation, please see below: