The TSMC InFO and CoWoS 3D packaging technologies enable customers to mix multiple silicon dice on a single device and achieve higher levels of integration and capacity than traditional monolithic ICs.
Based on the Mentor Calibre and Xpedition platforms, a full InFO design-to-package verification and analysis suite is now available from Mentor. Key benefits include a fast design-to-tape-out flow based on the Xpedition Package Integrator's rapid hierarchical design prototyping environment, with integrations to the Xpedition Package Designer and the Calibre sign-off verification suite. Additional collaboration extended the cross-probing capability between the Calibre 3DSTACK and Xpedition tools, with the results viewable within the Calibre RVE™ interface.
TSMC and Mentor also enabled the Mentor thermal flow (which includes the Mentor AFS and Calibre xACT™ offerings) to support thermal-aware simulation for customers' InFO designs.
To enable package-level cross-die timing analysis, Mentor enhanced Xpedition Package Integrator to support a netlisting capability incorporated with Calibre xACT extraction results for InFO and CoWoS designers to verify timing requirements.
Reliability is a fundamental component of all design flows. As such, TSMC and Mentor developed stacked-die solutions based on the Mentor Calibre PERC™ reliability platform for both TSMC's InFO and CoWoS flows. This new offering addresses inter-die electrostatic discharge (ESD) analysis.
"Our collaboration with Mentor supports mutual customers to quickly realize the benefits of using TSMC's InFO and CoWoS packaging solutions," said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. "With Mentor's design suite for TSMC InFO and CoWoS, customers in automotive, networking, high-performance computing (HPC), and numerous other markets can achieve new levels of integration."
"We are honored to be working alongside our longtime partner TSMC to further refine and mature Mentor design solutions for InFO and CoWoS packaging technologies," said Joe Sawicki, vice president and general manager, Mentor Design to Silicon. "Together we have helped make 3D-IC a viable mainstream alternative to monolithic IC design that is in enabling an ever-growing number of customers achieve truly remarkable world-changing innovations."
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Mentor Graphics Corporation, a Siemens business, is a world leader in electronic hardware and software design solutions, providing products, consulting services, and award-winning support for the world's most successful electronic, semiconductor, and systems companies. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. Web site: http://www.mentor.com.
Mentor Graphics, Mentor and Calibre, and Xpedition are registered trademarks and AFS, Calibre xACT, and Calibre PERC are trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owner.
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