UMC Qualifies Cadence Virtuoso LDE Analyzer for its 28HPCu Process
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UMC Qualifies Cadence Virtuoso LDE Analyzer for its 28HPCu Process

Highlights:

SAN JOSE, Calif., April 13, 2016 — (PRNewswire) — Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Cadence® Virtuoso® Layout-Dependent Effects (LDE) Analyzer has been qualified by United Microelectronics Corporation (UMC) to support its 28HPCU process technology. With the rollout of a new UMC 28HPCU LDE kit, UMC customers can use the Cadence solution to mitigate LDE in custom/analog designs, reducing post-layout iterations by up to 2X and accelerating design convergence by up to 40 percent.

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S.C. Chien, senior vice president and head of the IP Development and Design Support division at UMC, said, "We are pleased to add the Cadence Virtuoso LDE Analyzer to our 28HPCU design support portfolio. Transistor device characteristics vary with context, placement and density, and the Cadence LDE kit has allowed our customers who create designs using the 28HPCU process to seamlessly bridge the gap between their intended and expected results. This saves customers several steps in the design process to help them accelerate their designs to the production phase."

The collaboration between UMC and Cadence ensures that all of the following capabilities included with Virtuoso LDE Analyzer are fully enabled for the 28HPCU reference flow:

For more information about Cadence Virtuoso LDE Analyzer, visit www.cadence.com/news/virtuosolde.  

By using the UMC 28HPCU LDE kit, customers can take timely action to correct potential design issues. For example, designers can simulate LDE from a partial layout to integrate the LDE impact on device performance. In addition, they can check the consistency of device electrical properties without having to run simulation. They can also set LDE electrical matching constraints and run a single-click matching check during layout to ensure transistors match. Finally, designers can perform root-cause analysis early to find and fix differences before these differences cause the simulation to fail.

"We're collaborating with UMC to enable customers to diminish layout-dependent effects in custom/analog designs, and we've already been getting positive feedback from our mutual customers," said Dr. Anirudh Devgan, senior vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. "UMC customers using the Cadence Virtuoso LDE Analyzer no longer need to wait for a complete LVS-clean layout to include LDE in simulation, so they can be much more efficient."

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry. More information about the company, its products and its services is available at www.cadence.com.

© 2016 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and Virtuoso are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

For more information, please contact:
Cadence Newsroom
408-944-7039
newsroom@cadence.com

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SOURCE Cadence Design Systems, Inc.

Contact:
Cadence Design Systems, Inc.
United Microelectronics Corporation
Web: http://www.cadence.com