Hello and welcome to the first edition of the Cadence® System & Verification newsletter. In each issue, we'll share the latest news and events, recent product developments, and useful “how to” information that will help you improve your system design and verification productivity with the Cadence System Development Suite technologies and flows. Our aim is to aid you in getting to correct functionality and quality on time.

Please do send me your feedback on whether you find this newsletter valuable, and if there are any specific topics you'd like to see in future issues.

Thanks,

Michał Siwinski
VP, Product Management & Marketing
michal@cadence.com

An interconnect, also referred to as a bus matrix or fabric, serves as the communication hub of multiple intellectual property (IP) cores inside a system on chip (SoC). As the capacity of today’s SoCs continues to increase dramatically, interconnect verification complexity also grows, considering the master/slave numbers, various protocols, different kinds of transactions, and multi-layered topology. The traditional ways of firing many direct tests, or applying a divide-and-conquer strategy, do not provide a holistic verification for SoC interconnects. A systematic approach must be adopted to tackle the challenge and make the process more efficient. In this paper, we discuss how we adopted Cadence Verification IP for AMBA® Protocols and Cadence Interconnect Validator, an industry-leading tool for fabric verification. We convey how these tools helped us to improve verification efficiency, and we discuss a verification environment that we created with the Universal Verification Methodology (UVM). 

Taiwan-based fabless semiconductor company MediaTek is a leader in developing advanced systems on chip (SoCs) for wireless communications, HDTV, DVD, and Blu-ray, including ARM® -based systems such as the octa-core smartphone platform with LTE. The company’s corporate vice president, Andrew Chang, recently sat down with Cadence to talk about the development challenges of building advanced systems and how the company is using the Cadence Palladium® XP II platform to help create today’s smart devices. 

Watch this video to learn how MediaTek is meeting its time-to-market, power, and design quality goals with the Palladium XP II platform, part of the Cadence System Development Suite. 

By Adam Sherer – Product Marketing Director

When considering verification productivity, the focus should go beyond how fast a simulator can run, especially with large, complex SoCs. Simply cycling faster through the same data and the same analysis does not necessarily get you closer to closing verification. Geometric performance improvements are necessary, but insufficient to tame an exponentially growing problem.  Instead, add formal tools, abstract modeling tools, and metric-driven verification to a fast simulation engine to get past the clocks/second thinking. Ultimately, it’s all about moving swiftly toward next-generation productivity enhancements.   Find out more here!