PRINCETON, N.J. — (BUSINESS WIRE) — December 8, 2009 — Sarnoff Corporation, the leader in advanced embedded video processing, today introduced the Acadia^® II Development Platform (A2-DP-1). The A2-DP-1 provides a complete engineering platform for evaluating and integrating the capability of the Acadia II SoC, along with customer developed algorithms and system level processing. The Development kit offers an integrated platform combining the Acadia II SoC, including the embedded four-processor ARM11™ MPCore™, with a high performance Xilinx Virtex-5 FPGA for expandability.

The new development platform delivers access to the Acadia II video processing capabilities such as multi-band fusion, electronic stabilization, tracking and targeting, and real-time mosaics. While providing the necessary hardware and software to evaluate and implement the advanced features of the Acadia II, it also incorporates customer developed proprietary algorithms. This combination enables designers to incorporate complete system processing within the SoC, for platforms such as handheld and rifle mounted sights, EO/IR cameras, UAV/UGV’s, Military Vehicle SA, fire control systems, border/perimeter security, and ruggedized displays. The platform also supports industry-standard peripherals, connectors, and interfaces.

“Acadia II offers our customers a system-level processor with more power, smaller size, and less energy consumption than components they’re accustomed to working with,” said Mark Clifton, Sarnoff’s Acting President and Chief Executive Officer. “Sarnoff’s new Development Platform is ideal for those who are looking to prototype a new processing solution. It provides the ability to combine customer IP with the capability of the Acadia II SoC, into systems that are size, weight and power constrained, often reducing total system cost.”

Development Platform Contents

The A2-DP-1 is composed of the Acadia II SoC, Mezzanine Card, and Development board, and features:

• Acadia II Mezzanine board and SoC
  • Embedded quad ARM11^™ MPCore^™
  • 128 MB DDR2 SDRAM (1GB available as an option), 64 MB Flash
• Development Platform Board
  • Xilinx Virtex-5 XC5VLX110 FPGA with distributed and Block RAM
  • Configuration via JTAG or Config Flash
  • 4KB I2C PROM and FPGA Config Flash Memory
  • Switching power supply and step-down regulators
• Connectors/Accessories
  • Base Camera Link (3 inputs, 1 output)
  • Composite Video BNC (3 inputs)
  • VGA output
  • DVI-I connector
  • USB type A (2)
  • RS-232 (5)
  • 50 pin expansion connector
  • External power supply, (4) Camera link and (3) BNC video cables
• Documentation
  • Programmer’s Reference Manual
  • User’s Guide
  • Sample ARM Application with source code
  • Vision API documentation and libraries
  • Sample GUI Application with source code
  • Command Line Interface with source code
  • Schematics, BOM’s and Assembly Drawings