Cadence Announces National Semiconductor Adoption of Virtuoso Simulation Solution for Complex Analog Designs

SAN JOSE, CA -- (MARKET WIRE) -- Jul 15, 2009 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced today that National Semiconductor, developer of energy-efficient analog and mixed-signal semiconductors, has adopted the Cadence® Virtuoso® Accelerated Parallel Simulator to verify its large, complex analog designs. Verification engineers throughout National's global offices will have access to Cadence's high-capacity and scalable parallel simulation technology.

Introduced in December, the Accelerated Parallel Simulator is already proven for verifying large, complex analog designs -- with the complete accuracy of the Virtuoso Spectre® Circuit Simulator, and without a reduction in the design netlist. The capacity and scalability of the Accelerated Parallel Simulator shortens from weeks to days -- and in some cases hours -- the verification of complex designs.

"We are designing complex and large analog designs -- such as power management circuits, ADCs/DACs and SerDes -- that require advanced simulation technology with scalable performance across our multi-core compute platform, and without compromising accuracy," said Sury Maturi, director of the Design Automation Group at National Semiconductor. "After an extensive validation of the various simulation technologies on the market, we have selected the Accelerated Parallel Simulator. We were able to easily plug it in our current flow without changing our use model, and we've been getting impressive performance results without sacrificing accuracy."

Among the performance gains reported by National, the Virtuoso Accelerated Parallel Simulator, running on eight cores, delivered a 13.3X improvement for a step down DC-DC converter with 26,000 devices. It delivered a 17X performance gain for a post-layout multi-rate video clock generator with 270,000 devices when run on an eight-core multi-processing compute platform.

In addition, National achieved an additional performance boost with the parasitic reduction capability for post-layout analog IP dominated by parasitics.

"National Semiconductor's designs are just the type of medium to large complex designs that the Accelerated Parallel Simulator was developed to address," said Zhihong Liu, corporate vice president of Cadence. "Like our other customers, National's worldwide design centers have been able to reduce overall simulation time and meet ambitious tapeout schedules with the Virtuoso Accelerated Parallel Simulator."

The Virtuoso Accelerated Parallel Simulator is part of the Virtuoso Multi-mode simulation platform and delivers the full accuracy of the industry reference Cadence Virtuoso Spectre Circuit Simulator. Developed to solve the largest and most complex analog and mixed-signal designs across all process nodes, it consists of a combination of proven Cadence simulation technologies and a breakthrough parallel circuit solver along with a newly architected engine that efficiently harnesses the power of multiprocessing computing platforms. The result is a circuit simulator with an accuracy and use model identical to the Virtuoso Spectre Circuit Simulator, delivering significantly improved single-thread performance and scalable multi-thread performance.

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

Cadence, the Cadence logo, Spectre and Virtuoso are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

Add to Digg Bookmark with del.icio.us Add to Newsvine

For more information, please contact:
Dean Solov
Cadence Design Systems, Inc.
408-944-7226

Email Contact


Featured Video
Jobs
Business Development Manager for Berntsen International, Inc. at Madison, Wisconsin
GIS Specialist for Washington State Department of Natural Resources at Olympia, Washington
Mechanical Test Engineer, Platforms Infrastructure for Google at Mountain View, California
Manufacturing Test Engineer for Google at Prague, Czechia, Czech Republic
Machine Learning Engineer 3D Geometry/ Multi-Modal for Autodesk at San Francisco, California
Mechanical Manufacturing Engineering Manager for Google at Sunnyvale, California
Upcoming Events
URISA GIS Leadership Academy at Embassy Suites Fort Worth Downtown 600 Commerce Street Fort Worth, TX - Nov 18 - 22, 2024



© 2024 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering EDACafe - Electronic Design Automation TechJobsCafe - Technical Jobs and Resumes  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise