MOUNTAIN VIEW, California, and ELANCOURT, France - December 16, 2008 -
Esterel EDA Technologies today announced the release of Esterel Studio version 6.1, the leading front-end design and verification suite for control-intensive hardware IP, such as power management, memory controllers, peripheral cores, DMA, bus and peripheral interfaces, and processors of multimedia and wireless communication systems.

Version 6.1 includes new advanced and customizable formal verification strategies and comes with the first Verification Methodology Handbook describing all the verification processes enabling major productivity and quality gains throughout the design cycle. The Esterel v7 IEEE standardization project P1778 has proposed useful language improvements, many of which are already supported in this release. Other enhancements of this release include improved parametric IP design, modular SystemC code generation for large sub-systems, and C/C++ code performance improvements.

Esterel Studio comprehensive verification tools and supporting methodology allow Esterel Studio users to build powerful and reusable verification IP infrastructure. The Design Verifier is a formal verification engine implementing the most successful model-checking strategies for thorough and efficient debug. It enables to detect most block-level bugs during the design phase, saving many system-level RTL or SystemC costly validation iterations. With version 6.1 users can define customized combination of strategies, ways to group assertion goals, and select timeout criteria for maximal productivity. New assume and observe primitives enable to better capture design intent for formal verification. Verification code can now be written on side of the design without interfering in the code, while retaining ways to access internal signals and easily bind verification code to the design. The new cover primitive also enables to indicate functional coverage points and even to use the formal verification engine to generate input stimuli to reach these coverage points. The development environment generates scripts to perform all verification and coverage activities in batch, thus ensuring the most productive flow for the strongest possible confidence in design correctness.

The Verification Methodology Manual provides extensive guidance and best practice recipes to emphasize fast bugs discovery in early phases of design, or final proofs of correctness to secure the ESL to RTL sign-off. “We have seen our customers increase their usage of formal verification and appreciate its benefits in production project this year, especially thanks to our automatic assertions functionality that enables engineers with no prior knowledge to quick-start.”, says Günther Siegel, Esterel EDA Technologies CTO. “With the Verification Methodology Handbook, architects, design, and verification engineers can understand how to systematically derive assertions from specification and requirements, to maximize their benefits using the Design Verifier”.

The Esterel v7 IEEE standardization workgroup, an independent body of eighteen experts from fourteen industrial and academic organizations has reached consensus on language simplifications to increase designers’ productivity as well as enhance code readability and portability. Esterel EDA Technologies, committed to implement the standard has already included support of many such improvements in the commercial tool.

Esterel EDA Technologies also enriched its existing partnerships with CoWare® and Synfora with the recent addition of Atrenta, so that customers can deploy Esterel Studio version 6.1 within a complete and reliable ESL-to-RTL design flow. Indeed, coupling with CoWare Platform Architect enables to directly insert Esterel generated C++ code into virtual prototypes. Esterel generates controllers for all protocols supported by Pico Express™ generated pipeline architectures (PPA). Addition of Atrenta partnership enables to make sure that Esterel generated RTL is compatible with customers SpyGlass checking rules.

About Esterel Studio
Esterel Studio delivers the full benefits of ESL synthesis, providing an automated path from ESL to RTL by generating consistent VHDL/Verilog and SystemC implementations from a single and formally verified Esterel Studio IP executable specification. Esterel Studio includes an editor, a simulator, and supports assertions formal verification. Esterel Studio 6.1 is available in LAN and WAN configurations, with one-year time-based licensing starting at $50,000 USD.

About Esterel EDA Technologies
Esterel EDA Technologies is the supplier of Esterel Studio™, the leading solution for ESL synthesis, and a major provider of hardware, software and ESL design expertise to several top semiconductor companies. For additional information, visit the Esterel EDA Technologies website at www.esterel-eda.com.

Contact:
Günther Siegel, Esterel EDA Technologies
Phone: +33 (0)4 92 02 40 40
Email: Email Contact

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