The 300MHz SH77650 provides the same image-recognition processing functions as Renesas' existing 600MHz SH7774 high-performance SoC product for car navigation systems. The new chip is designed to deliver an excellent combination of cost, functionality and performance in driving-assist systems that perform functions such as white-line detection (lane-division recognition).
The device's intellectual property (IP) from Hitachi, Ltd. encompasses an image-recognition processing accelerator — specialized hardware that performs the computations necessary to identify road conditions via image data captured by a camera or similar device. The hardware accelerator can run multiple external image recognition programs such as roadway lane recognition or the detection and tracking of the cars and trucks ahead simultaneously and in real time. This capability makes it possible to realize sophisticated safety functions in a moving vehicle, such as adaptive cruise control. To facilitate the development of such applications, Renesas offers an image-recognition library containing approximately 200 functions. The new product also allows the reuse of existing engineering resources to save cost, including application software that customers had originally developed for the previous-generation product.
When operating at 300MHz, the SH-4A CPU core in the SH77650 achieves impressive processing performance: 540 MIPS (million instructions per second). Moreover, the SoC device's on-chip floating-point processing unit (FPU), which supports both single- and double-precision calculations, delivers 2.1 GFLOPS (giga floating-point operations per second) in single-precision mode at that speed. These high levels of performance enable the design of powerful image-recognition processing systems.
Besides the image-recognition processing accelerator, the SH77650 incorporates a variety of other on-chip peripherals required for automotive image-recognition applications. They include not only the requisite video input interface and display functions, but also a dedicated DMA controller, timers, a serial communication interface, and a CAN interface for in-vehicle LANs. An on-chip bus arbitrator supports three access priority levels so internal functions can access external memory efficiently. There is also a 32-bit dedicated external bus that can connect to high-speed DDR1-SDRAM (Double Data Rate 1 - Synchronous DRAM), and a 32-bit expansion bus that enables connections to external flash memory or SRAM. These on-chip peripheral functions and features allow this one chip to handle all of the main capabilities of an image recognition system. Thus, system engineers can produce designs that have fewer parts and cost less.
Development tools for the SH77650 SoC device include the previously mentioned image-recognition library, an emulator, and a reference platform. The E10A-USB emulator connects to a host PC via a USB bus, providing a real-time on-chip debugging capability at the SH77650’s 300MHz maximum operating frequency. The reference platform includes in-vehicle information-system oriented peripheral circuits and can be used as both a basic user system and a product verification environment. The platform is available now.
Price and availability
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| SH77650 (R8A77650DA01BGV) | 300MHz | 376-pin BGA | $51/ NOW |
