Revolutionary Constraint Management Technology Addresses AI Chip Design Challenges with 10x Memory Reduction and 20x Performance Boost

SAN FRANCISCO — (BUSINESS WIRE) — June 24, 2024 — DAC-CHIPS TO SYSTEMS CONFERENCE – Ausdia, the premier developer of design constraints verification and management solutions, introduced Timevision-HyperBlock (HB) at the 61st DAC, Chips to Systems Conference 2024.

Timevision-HB addresses the growing challenges faced by design teams in the AI era, including design sizes that push reticle limits, integration issues with large amounts of third-party IP and short time-to-market windows. The innovative HyperBlock technology uses an advanced abstraction system to create a minimal representation of SoC design blocks while retaining all critical information necessary for SDC constraint loading.

"We've spent the last several years perfecting this technology and ensuring it meets the performance and QoR (quality-of-results) requirements of our major customers," said Sam Appleton, CEO of Ausdia Inc. "On leading-edge AI designs, we see up to 10x reduction in memory consumption and up to 20x increase in performance for constraint management tasks, including SDC constraint promotion and demotion. We're delighted to introduce this technology at a time when design size and the use of 3D-IC technology is exploding."

Timevision-HB supports both gate-level netlist and RTL designs, enabling a "shift-left" design methodology for even the largest SoCs in the industry. The HyperBlock models can be easily loaded into an SoC top-level – where all the major components of the SoC are brought together and connected – with all information necessary to load the SDC and other constraints retained in the HyperBlock model. This abstraction technology significantly reduces the size of the in-memory design and the complexity of SDC constraint operations.

In addition to Timevision-HB, Ausdia has enhanced its toolkit with more than 25 additional signoff constraint checks. The company has also introduced a new feature called "SDC Audit," which automates the previously manual and time-consuming process of final stage constraint set auditing, making it reproducible and reusable.

Timevision is a comprehensive timing constraints development, verification, and management solution that complements all implementation and timing signoff flows. It has the capacity to handle over 1 billion cells and thousands of clocks. Timevision integrates with all aspects of the design flow and is used before synthesis, before DFT insertion, before place and route, and when signoff timing is being run.

Ausdia is showcasing the Timevision platform, including the new HyperBlock technology, at #2310 at DAC at the San Francisco Moscone Convention Center, San Francisco, CA from June 23 - 27, 2024.

About Ausdia

Ausdia delivers standout timing constraint development, verification, and management solutions that complement all implementation and timing signoff flows. The company's groundbreaking methodology and products give system-on-chip (SoC) and integrated circuit (IC) developers a new way to work, enabling massive productivity gains throughout the design flow. Founded in 2006, the privately held company is headquartered in Sunnyvale, California.

Ausdia acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

View source version on businesswire.com: https://www.businesswire.com/news/home/20240624903237/en/

For more information, please contact:
Michelle Clancy Fuller, President, Cayenne Global
Michelle.clancy@cayenncom.com
+1 503.702.4732