Embargoed until 09:00 on Friday 11ht November 2022
Cryogenic CMOS design enabled by Semiwise
Semiwise has developed transistor SPICE models based on the GlobalFoundries (GF) 22FDX® Platform that enable cryogenic CMOS design and verification. Using its patented ‘re-centring’ technology Semiwise has developed models for typical (TT) fast (FF) and slow (SS) transistor corners. Using the Semiwise tool RECENTER, the models can be seamlessly included in the standard EDA tool flow based on the GF 22FDX Platform Process Design Kit (PDK).
The Semiwise ‘re-centring’ technology includes combination transistor measurements and TCAD simulations using the cryogenic-proven Synopsys Sentaurus™ device simulator. The ‘re-centring’ process is automated using the Synopsys TCAD-to-SPICE flow, which is part of the Synopsys Design Technology Co-Optimization (DTCO) tool chain.
Design of cryogenic CMOS chips is vital for the scaling of different types of quantum computers to accommodate the large number of quantum bits (q-bits) needed for solving real-life problems. The current bottleneck is related to the very low temperature (anywhere from 77K to a fraction of a Kelvin) of operation of the q-bits housed in cryostats. Many cables take information from the q-bits to room-temperature CMOS chips outside of the cryostat that read, condition and process the ‘quantum’ information, making the quantum computer look like a Christmas tree. As a result, only relatively small numbers of q-bits can be housed in a single large cryostat.
The Semiwise models can also be used to design COLD CMOS chips for data centres that can operate at liquid nitrogen temperatures. A recent study from Synopsys shows that if processors and other chips are operated at 77K, the power dissipation can be reduced ~7x at equivalent speed.
This temperature reduction results in drastic changes of the transistor characteristic, rendering room-temperature chip design and the corresponding chip technologies unsuitable for cryogenic chip operation. Most of the current technologies require significant re-optimization to enable cryogenic chip operation. However, in the GF 22FDX Platform, the transistor parameters can be flexibly altered by electrical (back) biasing to compensate for the low temperature changes. This makes the technology directly applicable to cryogenic chip design as it stands.
According the Semiwise CEO Professor Asen Asenov, “The cryogenic chip design will not only unleash the true power of quantum computers but will increase significantly the energy efficiency of the data centres in the transition to a net zero economy.”
About Semiwise: SemiWise ( https://www.semiconductorwise.com/) develops innovative low-power CMOS transistor-level IP that improves performance and variability, and drastically reduces power consumption. SemiWise also offers simulation services and consulting to the semiconductor industry including fables, IEDM and foundry players. The CEO of Semiwise, Professor Asenov was the founder of Gold Standard Simulations (GSS), a 2010 startup from the University of Glasgow which developed the first TCAD based Design-Technology Co Optimisation (DTCO) tool chain. After the acquisition of GSS by Synopsys in 2016 the TCAD-to-Spice technology originally developed by GSS is now part of the Synopsys TCAD offering in the so called TCAD-to-Spice flow:
https://www.synopsys.com/silicon/tcad.html.
This technology will be used in the Cryogenic PDK re-centering.
Contacts:
asen.asenov@glasgow.ac.uk,
+44 07523 293 782
Related press releases:
https://www.embedded.com/cryo-cmos-ip-enables-qubit-control-chips-at-cryogenic-temperatures/
https://www.eenewseurope.com/news/surecore-expands-control-logic-quantum-computing?fnid=140205
Note: Professor Asenov is also a Director of Surecore.
