- Rambus uses Avery’s high-quality, full-featured memory model to verify its HBM3 PHY and controller.
- Rambus includes these memory models in its customer deliveries to enable out-of-the-box simulations with the delivered IP.
- Customers can then license the Avery memory models for use in full SoC verification
Tewksbury, MA – December 8, 2021 – Avery Design Systems, a leader in functional verification solutions, today announced comprehensive support for the new HBM3 interface standard. Rambus uses Avery’s high-quality HBM3 memory models to verify the new Rambus HBM3 Memory Subsystem.
The Rambus HBM3 Memory Subsystem, comprised of an HBM3 PHY and HBM3 Controller, is optimized for systems that require a high-bandwidth, low-latency memory solution. This includes applications in AI/ML training, graphics and high-performance computing (HPC). The subsystem supports data rates up to 8.4 Gbps per data pin and features 16 independent channels, each containing 64 bits for a total data width of 1024 bits. At maximum data rate, this provides a total interface bandwidth of 1075.2 GB/s.
Rambus uses Avery’s high-quality, full-featured memory model to verify its HBM3 PHY and controller. Rambus includes these memory models in its customer deliveries to enable out-of-the-box simulations with the delivered IP. Customers can then license the Avery memory models for use in full SoC verification.
“We deliver fully integrated and verified memory subsystems in order to meet our customers’ time-to-market and quality demands. Avery has been a trusted partner and plays a critical role in helping us to ensure our memory subsystems perform as promised,” said Brian Daellenbach, senior director of Memory & MIPI Controllers, Interface IP at Rambus.
Avery offers a complete functional verification platform based on its robustly tested verification IP (VIP) portfolio that enables pre-silicon validation of design elements. Its HBM3 offering includes memory models, protocol checkers, performance analysis, and compliance test-suites utilizing a flexible and open architecture. HBM2E and HBM3 speed adapters are also available for FPGA prototyping platforms.
“Our mutual customers need early access to verified models of the latest standards, as well as a verification platform to enable a reliable verification methodology. Our collaboration with Rambus allows developers to stay ahead of the curve as new standards emerge. We are pleased to be able to deliver an HBM3 verification solution, which enables our customer to develop compute-intensive SoCs in advanced processes with confidence," said Chris Browy, vice president of sales/marketing at Avery.
About Avery Design Systems
Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for gate-level X-pessimism verification and real X root cause and sequential backtracing; and robust core-through-chip-level Verification IP for PCI Express, CXL, CCIX, Gen-Z, USB, AMBA, UFS, MIPI CSI/DSI, I3C, DDR/LPDDR, HBM, ONFI/Toggle/NOR, NVM Express, SATA, AHCI, SAS, eMMC, SD/SDIO, CAN FD, and FlexRay standards. The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.
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