UVM-based Verification of Custom Instructions with RISC-V Cores
Presenter: Roddy Urquhart, Senior Marketing Director, Codasip
Thursday, September 17, 2020
Abstract:
By integrating Aldec’s Riviera-PRO™ with Codasip’s Studio™, verification of RISC-V CPU custom instructions at the RTL implementation level becomes an incredibly powerful platform for RISC-V processor deployment.
In this presentation, we will show in Studio, how users can describe the RISC-V architecture and add custom instructions using CodAL high level language, modify the pipeline, configure random instruction generator, auto-generate the HDK, SDK, RTL implementation and C++ reference model and UVM environment, start RTL simulation, setup breakpoints and debug.
We will then show in Riviera-PRO, how users can run RTL simulation and debug applications and core architecture, inspect simulation waveforms, use the UVM Graph & Toolbox to view the graphical representation of the UVM components, objects and the transaction level modeling (TLM) connections between them, giving the user an overall perspective of the testbench architecture and the dataflow. We will also show how you can collect and analyze both functional coverage and code coverage.
Agenda:
- RISC-V Custom Instructions
- Customization with Codasip Studio
- RISC-V Core Verification Requirements
- UVM-based simulation with Riviera-PRO
- Conclusion
- Q&A
Event Info
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Roddy Urquhart, Senior Marketing Director, Codasip
Roddy has over 35 years experience in semiconductor, EDA and IP companies and has worked in marketing, sales, general management and engineering roles. He has a Ph.D. from the University of Glasgow.
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Zdenek Prikryl, Chief Architect, Codasip
Dr. Prikryl has undertaken research at Brno University of Technology which led to the creation of processor development tools at Codasip. Specifically, he was a developer of the methodology to automatically generate hardware and software development kits from a processor description language. Dr Prikryl has been chief architect of Codasip Studio for over ten years and has been the architect of diverse processor cores including but not limited to 16/32-bit architectures for IoT, 32/64bit DSP oriented architectures or Linux capable architectures. All of these architectures were developed using Studio and many of them were based on RISC-V ISA.
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Michal Pacula, Technical Support Manager, Aldec
Michal joined Aldec in 1998 and worked in a wide range of positions that include Application Engineer and SQA Manager responsible for Active-CAD, Active-HDL and Riviera-PRO products. Michal’s practical experience includes Digital Design, Verification Methodologies and a deep understanding of HDL modeling. Michal graduated with M.S. in Electronic Engineering (EE) at the Silesian University of Technology in Gliwice, Poland.
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