RISC-V Soft CPU Contest, sponsored by Microchip Technology and Thales, challenges designers to drive technology innovation forward with the free and open RISC-V ISA
BERKELEY, Calif. — (BUSINESS WIRE) — July 15, 2019 — The RISC-V Foundation, a non-profit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), today announced the call for submissions for the RISC-V Soft CPU Contest. The aim of the contest is to challenge designers to develop a hardware secure RISC-V soft CPU solution that can thwart malicious software security attacks. The contest is sponsored by RISC-V Foundation members Microchip Technology Inc. and Thales.
“With the proliferation of connected devices, security is one of the key challenges in hardware design. The free and open RISC-V ISA presents an incredible opportunity for the ecosystem to collaborate to develop more robust solutions for the growing security demands of today and the future,” said Calista Redmond, CEO of the RISC-V Foundation. “This contest is an opportunity for designers and hardware enthusiasts to rethink what is possible with computing design and build a secure RISC-V soft CPU that can prevent software security attacks.”
The contest targets the Creative Development Board using Microchip’s 25K LUT IGLOO™ 2 FPGA available at Future Electronics for $149.95.
Thales will evaluate the nominations and select the top three winners overall. Judges will review how many of the five security attacks are thwarted, in addition to evaluating the total resources used, including logic elements, math blocks and internal RAM, as well as CPU core FMAX, expected power consumption and the amount of changes to the compiler. The prizes that will be awarded are:
First place prize: Second place prize: Third place prize: |
5000€ + HiFive Unleashed + HiFive Unleashed Expansion Board 2000€ + HiFive Unleashed 1000€ + HiFive Unleashed |
The deadline for entries is Sept. 15, 2019 at Midnight CET. To submit, contest participants must email Email Contact with links to their relevant GitHub repositories, including the zipped FPGA files and compiler. To read more about the contest details and rules, please visit: https://riscv.org/2019/07/risc-v-softcpu-core-contest/.
The winning entries will be announced at the Getting Started with RISC-V event in Paris on Sept. 24, 2019. Contest participants do not have to be in attendance to be eligible to win. To learn more about the Getting Started with RISC-V European roadshow and register, please visit: https://events.linuxfoundation.org/events/risc-v-europe-roadshow-2019/.
Supporting Resources
- Visit RISC-V Foundation: https://riscv.org/
- Follow RISC-V Foundation on Twitter: @RISC_V
- Follow RISC-V on LinkedIn
- Become a member today
About RISC-V Foundation
RISC-V (pronounced “risk-five”) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 250 members building the first open, collaborative community of software and hardware innovators powering a new era of processor innovation. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem.
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Contact:
Allison DeLeo
Racepoint Global for RISC-V Foundation
Phone: +1 (415) 694-6700
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