Realtek Deploys IC Compiler II for Its Next-generation Communications Network Design

Highlights:

• IC Compiler II 2019 release delivers up to 2X faster throughput with next-generation distributed parallelization, intelligent scenario management, efficient infrastructure scaling, and inherent core engine algorithm acceleration
• Innovative power reduction technologies, including predictive total power optimization, IR Drop-driven optimization, and dynamic voltage-driven clock scheduling, result in 10 percent lower total power
• Next-generation arc-based unified CCD optimization, enhanced register pipelining, topological interconnect planning, and physically-aware logic re-synthesis delivers 5 percent area and timing improvement

Synopsys, Inc. (Nasdaq: SNPS) today announced immediate availability of the latest release of its flagship IC Compiler^™ II place-and-route system that includes several new innovative technologies to deliver superior quality-of-results (QoR) and fastest time-to-results (TTR) for the next wave of leading-edge designs across a wide range of vertical markets, including automotive, cloud computing, AI, networking and wireless applications. Continued investment in technology advancements in IC Compiler II technologies deliver ten percent total power reduction, five percent smaller area, five percent better timing, and 2X faster runtime. Based on observed benefits, Realtek has deployed the latest IC Compiler II technologies on their next-generation communication network designs to meet stringent power, performance, and area (PPA) budgets while speeding up TTR for their designs.

"Designing some of the most complex network communications devices and achieving the highest QoR without compromising our design schedule is absolutely critical for us in our target markets," said Realtek's vice president and spokesman, Yee-Wei Huang. "We have collaborated closely with Synopsys in deploying the latest IC Compiler II technologies and have observed up to 2X runtime speed-up. We are confident that we can effectively meet our aggressive QoR and time-to-market goals."

Key new technologies in IC Compiler II for superior QoR include a common physical optimization infrastructure, new arc-based unified concurrent clock-and-data (CCD) optimization, physically-aware logic re-synthesis, and dynamic voltage drop-driven power shaping. RedHawk^™ Analysis Fusion IR drop-driven optimization, exhaustive path-based analysis (PBA), and signoff accuracy within IC Compiler II result in unmatched design convergence. Several new speed-up improvements, including inherent core engine algorithm speed-up, intelligent scenario management, efficient hardware scaling, and flow concurrency, deliver 2X faster design throughput.

"The IC Compiler II place-and-route solution is the preferred tool of choice for complex next-generation designs where pushing PPA boundaries is critical," said Sassine Ghazi, general manager of the Design Group at Synopsys. "Customers like Realtek are at the forefront of innovation, and their adoption of the latest IC Compiler II release is a testament to how Synopsys' place-and-route solution is leading the industry in QoR and helping them deliver differentiated products."

About Synopsys

Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software^™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 15^th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest security and quality, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.

Editorial Contact:
James Watts
Synopsys, Inc.
650-584-1625
jwatts@synopsys.com

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SOURCE Synopsys, Inc.