The 2019.3 release of Aldec’s Spec-TRACER™ boosts the efficiency of teams designing for safety-critical applications for which complete traceability must be provided.
HENDERSON, Nev. — (BUSINESS WIRE) — April 1, 2019 — Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has enhanced its popular unified requirements lifecycle management EDA tool, Spec-TRACER™, to better support team-based projects when working on designs that must be certified to safety standards such as DO-254. The 2019.3 release contains a relational database, in order to support multiple users at once, within which there are repositories of project examples.
“Spec-TRACER has always supported team-based workflows and methodologies, but it was necessary to manually add and then configure an SQL database to run in the background,” comments Janusz Kitel, DO-254 Program Manager at Aldec. “The inclusion of a database in the 2019.3 release of Spec-TRACER negates the need for such integration and the team can focus on meeting their traceability management responsibilities, which are now made easier by the fact the database contains project examples.”
Other new features include a Comma Separated Value (CSV) parser for capturing traceability data from more source documents, the Aldec Coverage Database (ACDB) parser for capturing the verification plan together with coverage results, and an IBM DOORS parser for capturing traceability links and hierarchical relationships. Also, modifications made in external documents and captured by the Spec-TRACER parser can now be easily observed against the previous version.
Spec-TRACER continues to provide users with a choice on where artifacts, such as design data, functional specifications and project documentation, are maintained; either in the native editors - such as a text editor, Word, Excel or a DOORS module - or within Spec-TRACER. Regardless of the maintenance location, users will benefit from Spec-TRACER’s change management, traceability verification, reviews and reporting features.
About Aldec
Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com
Aldec is a registered trademark of Aldec, Inc. All other trademarks or registered trademarks are the property of their respective owners.
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