In addition, core components of the Calibre suite have been enabled for the Samsung 7LPP process technology using EUV lithography, including Calibre nmDRC™, Calibre nmLVS™, Calibre xACT™, and Calibre PERC™ software. These Calibre design kits can be used for initial test chips and intellectual property (IP) creation on the Samsung 7LPP process technology.
"Samsung Foundry continues to offer the most competitive process technology in the industry. Our collaboration with Mentor ensures the availability of qualified tools that enable our mutual customers to develop designs that best leverage the Samsung Foundry's process offerings," said Jaehong Park, senior vice president of the Foundry Design Team at Samsung Electronics. "The Mentor tool enablement for our 8LPP and 7LPP is a demonstration of our long-term partnership that continuously strives to enable designers to implement, verify, test, and deliver designs with confidence."
Samsung has enabled multiple tools in the industry-leading Calibre platform for the 8LPP process technology to ensure designers can achieve tapeout success quickly and confidently.
- The Calibre nmDRC and Calibre nmLVS tools help design teams verify and optimize their designs to meet Samsung 8LPP process requirements, providing innovative and accurate physical and circuit verification that address the growing layout complexity and exacting performance requirements of advanced node designs.
- Calibre Pattern Matching functionality enables designers to apply a variety of visual geometry analyses to quickly and accurately perform complex verification tasks, such as the verification of precise configuration requirements across multiple instances, and lithographic hotspot identification.
- The Calibre xACT platform delivers unparalleled parasitic extraction accuracy and performance, automatically using an integrated field solver to calculate parasitics with attofarad accuracy for complex three-dimensional structures, while implementing a highly scalable parallel processing approach to optimize performance for multi-million-instance designs.
- The Calibre PERC reliability platform employs a unique integrated analysis of both the physical layout and the netlist to automate complex reliability checks.
- The Calibre YieldEnhancer product—specifically its SmartFill and engineering change order (ECO)/timing-aware fill capabilities—helps designers control design planarity through multiple design changes across intellectual property (IP), blocks, and the full chip, to ensure designs comply with manufacturing planarity requirements and meet tapeout schedules. It also enables designers to implement layout enhancements (such as via optimization) to improve manufacturing success.
- The Calibre LFD™ tool—based on Mentor's production-deployed solutions for process-window modeling, mask synthesis, optical proximity correction (OPC), and resolution enhancement (RET)—accurately models the impact of lithographic processes to predict actual "as-manufactured" layout dimensions, identifying potential lithographic issues and enabling designers to optimize yield and product reliability.
- As design teams simultaneously address multiple design for manufacturing (DFM) options, they can use the Samsung DFM scoring and analysis solution with the Calibre YieldAnalyzer tool to streamline the process of making tradeoff decisions, such as via redundancy checking. Samsung also supports yield detractor pattern identification and repair incorporating the Calibre Pattern Matching solution to provide fast feedback from manufacturing results to customer design processes. To further enable customers to quickly find and address DFM issues, Mentor and Samsung also announced the availability of the Calibre DFM Explorer functionality.
To enable system-on-chip (SoC) designers to complete circuit verification, physical implementation, and IC test with confidence, the AFS platform is enabled in Samsung's 8LPP device models and design kits. Our mutual customers rely on the AFS platform to deliver nanometer SPICE accuracy while verifying analog, RF, mixed-signal, memory, and custom digital circuits faster than with traditional SPICE simulators.
The Nitro-SoC P&R system is enabled for netlist-to-GDSII physical implementation in the Samsung 8LPP process technology. A wide range of innovative technologies, including advanced design rule checking (DRC) avoidance on multi-patterning routing layers, mask and layer optimization for convergent timing, and smart library pin access capabilities are supported for optimized power/performance/area (PPA) results on this technology node. Customers have access to features like multi-corner multi-mode (MCMM)-based area optimization, comprehensive multi-VDD-based low power flow, native integration with Calibre sign-off, and comprehensive parallelization for a faster turnaround time.
"Our partnership with Samsung Foundry is not just a matter of providing tools that meet minimum requirements," stated Joe Sawicki, Vice President and General Manager of the Mentor Design-to-Silicon Division. "The joint solutions we deliver enable our mutual customers to fully leverage Samsung's process offerings for success in both initial tapeouts and silicon production, providing a vital link between fabless companies and Samsung Foundry."
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Mentor Graphics Corporation, a Siemens business, is a world leader in electronic hardware and software design solutions, providing products, consulting services, and award-winning support for the world's most successful electronic, semiconductor, and systems companies. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. Website: http://www.mentor.com.
Mentor Graphics, Mentor, and Calibre are registered trademarks, and Analog FastSPICE, Nitro-SoC, nmDRC, nmLVS, xACT, PERC, and LFD are trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owner.
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SOURCE Mentor, a Siemens business
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