End-to-End Tool Suite Analyzes, Augments, Verifies Functional Safety of SoC, ASIC, IP Designs

AUSTIN, TEXAS –– May 23, 2017 –– Austemper Design Systems today unveiled the semiconductor industry’s first end-to-end tool suite to analyze, augment and verify functional safety in system-on-chip (SoC), application specific integrated circuit (ASIC) and intellectual property (IP) designs ensuring they meet functional safety requirements.

“Functional safety is a challenge shared by the automotive, medical, industrial and enterprise markets, and is currently a manual process that doesn’t scale,” says Sanjay Pillay, founder and chief executive officer of Austemper. “Our goal is to meet the challenge with a cost-effective and comprehensive one-stop solution with all the pieces of the functional safety puzzle in an automated and repeatable fashion that meets a variety of certification-oriented applications.”

Austemper will demonstrate its Functional Safety Tool Suite at the Design Automation Conference (DAC) in Booth #1420 June 19-21 from10 a.m. until 6 p.m. at the Austin Convention Center in Austin, Texas.

Introducing the Semiconductor Industry’s First Functional Safety Tool Suite

Austemper’s Functional Safety Tool Suite includes SafetyScope for safety analysis, Annealer and RadioScope to handle safety synthesis and augment design structures, and KaleidoScope for safety verification. An engineering group would start with SafetyScope to implement functional safety estimates based on a mission profile and set of diagnostic coverage mechanisms. SafetyScope automatically applies default values from industry standards ISO26262 and/or IEC61508 for Failures-in-Time (FIT) rates and other diagnostic coverage metrics. It can be used for analog, digital or mixed-signal designs and can be integrated with existing electronic design automation (EDA) flows. It runs hierarchically and scales to multi-million gate designs. SafetyScope supports System Verilog, Verilog, VHDL and Netlist designs.

The engineering group would move on to Annealer to automate the formerly manual, error-prone approach of adding fault tolerance to a design’s storage elements and hardening the design. Annealer can handle memories, register files, FIFOs or entire processing units.

RadioScope provides fine-grained safety synthesis capabilities. Like macro-oriented Annealer, it offers automated fault-detection insertion and tolerance methods targeting state elements in the design and cones of synthesizable logic.

Annealer and RadioScope support System Verilog, Verilog and netlist designs to accommodate a variety of designs and tool flows, as well as multi-clock designs. The synthesis tools have the ability to auto-recognize design structures. Annealer recognizes memory macros, while RadioScope recognizes finite state machines (FSMs) and other control structures. For state elements, RadioScope can auto-group elements to generate parity and engineering change orders. Both provide self-checking for inserted functional safety enhancements as testbenches and test scripts to highlight automated changes introduced into the design. The output is tool-agnostic and integrates with any universal verification methodology (UVM)-compliant simulation framework. They also generate SEC/LEC scripts to show the original design intent was preserved and meets ISO requirements of traceability and fault tolerance.

The final step is KaleidoScope, the industry’s only parallel fault simulator with hybrid simulation capabilities. Traditional fault-injected simulation models inject faults into the synthesized netlist and run exhaustive gate-level simulations that take months. KaleidoScope removes the bottleneck by decoupling the simulator from fault injection by taking in the design file with an industry-standard value change dump (VCD) format file. Its patent-pending technology runs multiple fault simulations in parallel to model permanent or transient single-point or multi-point faults for a 100x speedup, reducing the fault verification cycle from months to days.  KaleidoScope supports System Verilog, Verilog, VHDL and netlist designs.

Availability and Pricing

The Austemper Functional Safety Tool Suite is shipping now and has been adopted by functional safety architects, design and verification teams worldwide with automotive applications demonstrating reliable, repeatable and verifiable functional safety. Austemper has a direct sales channel in the United States and Europe, backed by a variety of customer support and service options including on-site training, hotline support and consulting services.

Pricing is available upon request.

About Austemper

Austemper Design Systems provides the industry’s only end-to-end tool suite to analyze, augment and verify functional safety in system-on-chip (SoC) and application specific integrated circuit (ASIC) and intellectual property (IP) designs, ensuring they meet functional safety requirements. Austemper of Austin, Texas, was founded in 2015 by experienced semiconductor professionals with the mission to provide a best-in-class solution to meet functional safety requirements of the automotive, industrial, medical and enterprise markets.  For more information, visit: www.austemperdesign.com

Contact:

Nanette Collins
Public Relations for Austemper Design Systems
(617) 437-1822
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