Cambricon Licenses Arteris FlexNoC Interconnect IP for Machine Learning SoCs

Highly scalable fabric IP is key to accelerating machine learning

CAMPBELL, Calif. — April 18, 2017 — ArterisIP, the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced that Cambricon has licensed  Arteris FlexNoC interconnect IP for use as the backbone interconnect of their revolutionary machine learning SoC.

Cambricon is a startup company focusing on artificial intelligence (AI) and machine learning. Targeting all AI markets, Cambricon products can be applied to mobile phones, surveillance cameras, high performance servers, and other systems. Enabling neural network processing efficiency and capacity improvements, Cambricon technology drastically improves the processing of deep learning algorithms for all end markets and devices.

“After a rigorous evaluation of nearly all commercial solutions, we determined that Arteris FlexNoC interconnect IP was the only NoC technology that would meet all our requirements.” said Dr. Daofu Liu, Vice President at Cambricon. “The Arteris IP is easy to configure and has been proven in many silicon chips, which allows us to reduce development time and manage project risk.”  

“Arteris is honored to be chosen to support Cambricon in pushing the technical state-of-the-art of neural network processing,” said K. Charles Janac, President and CEO of Arteris. “Both our technologies are foundational to the advancement of machine learning processing that drives evolving capabilities in areas utilizing artificial intelligence.” 

About ArterisIP 

ArterisIP provides  system-on-chip (SoC) interconnect IP to accelerate SoC semiconductor assembly for a wide range of applications from IoT to mobile phones, cameras, automobiles, SSD controllers and servers for customers such as  SamsungHuawei / HiSiliconMobileyeAltera (Intel), and  Texas Instruments. ArterisIP products include the  Ncore cache coherent and  FlexNoC non-coherent interconnect IP, as well as optional  Resilience Package (functional safety) and  PIANO automated timing closure capabilities. Customer results obtained by using the ArterisIP product line include lower power, higher performance, more efficient design reuse and faster SoC development, leading to lower development and production costs. For more information, visit  www.arteris.com.

 

Contact:

Kurt Shuler
ArterisIP
+1 408 470 7300
Email Contact

Featured Video
Jobs
Principal Engineer for Autodesk at San Francisco, California
Manufacturing Test Engineer for Google at Prague, Czechia, Czech Republic
Equipment Engineer, Raxium for Google at Fremont, California
Senior Principal Software Engineer for Autodesk at San Francisco, California
Senior Principal Mechanical Engineer for General Dynamics Mission Systems at Canonsburg, Pennsylvania
Mechanical Manufacturing Engineering Manager for Google at Sunnyvale, California
Upcoming Events
Intergeo 2024 at Messe Stuttgart Messepiazza 1 Stuttgart Germany - Sep 24 - 26, 2024
GIS-Pro 2024 at Portland ME - Oct 7 - 10, 2024
Geo Sessions 2024 at United States - Oct 22 - 24, 2024



© 2024 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering EDACafe - Electronic Design Automation TechJobsCafe - Technical Jobs and Resumes  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise