LOUISVILLE, Colo., March 06, 2017 (GLOBE NEWSWIRE) -- The 2017 Design and Verification Conference and Exhibition U.S. (DVCon U.S.), sponsored by Accellera Systems Initiative, concluded last week with attendees inspired by the many in-depth technical tutorials, panels, poster sessions and keynote address offered during the four-day program. The sold-out DVCon Exposition was a gathering place for many attendees in the afternoon to share ideas and connect with colleagues.
Overall attendance, including exhibit-only and technical conference attendees, was 775. Attendance was further enhanced by 276 exhibitor personnel that also had access to the panel sessions and keynote address, for a total of 1,051 participants.
“In its 29th year, DVCon U.S. 2017 concludes another successful conference,” said Dennis Brophy, DVCon U.S. General Chair. “DVCon’s popularity to the practicing design and verification engineer has led to a global expansion of the conference to four venues around the world with more than 2,000 attendees this past year. As we share best practices on electronic system design and verification, and foster discussion on current and emerging standards and technology, the DVCon conferences have become the must-attend events to learn about state-of-the-art methods.”
The Award for Best Paper Presentation, as voted by conference attendees, went to Stan Sokorac, ARM, Inc. for his presentation titled, “Optimizing Random Test Constraints Using Machine Learning Algorithms.” Second place was awarded to Eldon Nelson, Intel Corp. for his presentation, “Improving Constrained Random Testing by Achieving Simulation Verification Goals through Objective Functions, Rewinding and Dynamic Seed Manipulation,” and third place was awarded to Honghuang Lin, Zhipeng Ye and Asad Khan, Texas Instruments, Inc. for their presentation, “Machine Learning based PVT Space Coverage and Worst Case Exploration In Analog and Mixed-Signal Design Verification.”
Top honors for Best Poster went to Johannes Schreiner, Felix Willgerodt and Wolfgang Ecker, Infineon Technologies for their poster, “A New Approach for Generating View Generators.” Second place was awarded to Daniel Hansson and Patrik Granath, Verifyter AB for their poster, “Automatic Debug Down to the Line of Code,” and third place was awarded to Jacob Maas, Nirabh Regmi, Ashish Kulkarni and Krishnan Palaniswami, Microsoft Corp. for their poster, “End to End Formal Verification Strategies for IP Verification.”
“We congratulate our Best Paper and Best Poster Winners for 2017,” stated Tom Fitzpatrick, DVCon U.S. Program Chair. "When you consider the high quality of the papers and posters accepted for the DVCon U.S. technical program, being judged one of the ‘best of the best’ is quite an accomplishment. We are very proud of the breadth and depth of the papers and posters submitted on such a broad range of leading-edge topics to create such an exciting conference for our attendees. I would also like to thank my colleagues on our Technical Program Committee for their untiring efforts in working with our authors to ensure that all papers and presentations provide the level of technical information that our attendees have come to expect when they come to DVCon.”
Highlights of the Week:
Accellera Day opened the conference on Monday morning to a packed audience eager to learn more about the emerging Portable Stimulus standard. Tom Alsop, a Principal Engineer at Intel, was recognized during the Accellera-sponsored luncheon as the recipient of the sixth annual Accellera Technical Excellence Award. He served as co-chair of the Universal Verification Methodology (UVM) Working Group for eight years and is currently chair of the IEEE P1800.2 UVM Working Group.
On Tuesday Dr. Anirudh Devgan, Senior Vice President and General Manager of the Digital & Signoff Group and System & Verification Group at Cadence, delivered the keynote, “Tomorrows Verification Today,” and Harry Foster, Chief Scientist for Mentor Graphics, presented a special session, “Trends in Functional Verification: A 2016 Study” that provided some invaluable insight into the state of today’s electronics industry. For a copy of either presentation, visit the DVCon U.S. homepage.
There were two panels on Wednesday. The first panel, “Users Talk Back on Portable Stimulus” provided some lively discussion regarding how to shape and get involved in the development of the emerging standard. The second panel, “SystemVerilog Jinxed Half My Career: Where Do We Go from Here?” was well-attended and offered interesting perspectives on the impact of the standard.
Thursday provided attendees with a full day of sponsored technical tutorials to choose from.
The DVCon Steering Committee values all feedback regarding the conference. Attendees have been given a survey and are asked to provide input on how to make DVCon U.S. 2018 even better.
Save the date: DVCon U.S. 2018 will be held February 26-March 1 at the DoubleTree Hotel in San Jose, California. DVCon China 2017 will be held April 19 in Shanghai, China; DVCon India 2017 will be held September 14-15 in Bangalore, India; and DVCon Europe 2017 will be held October 16-17 in Munich, Germany.
About DVCon
DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies. In response to global interest, in addition to DVCon U.S., Accellera also sponsors
DVCon China,
DVCon Europe and
DVCon India. For more information about Accellera, please visit
www.accellera.org. For more information about DVCon U.S., please visit
www.dvcon.org. Follow DVCon on Facebook
https://www.facebook.com/DVCon or @dvcon_us on Twitter or to comment, please use #dvcon_us.
For more information, please contact: Nannette Jordan MP Associates, Inc. 303-530-4562 nannette@mpassociates.com Barbara Benjamin HighPointe Communications 503-209-2323 barbara@hipcom.com
