- QuickLogic has completed its production qualification for the new EOS S3 ultra-low power sensor processing SoC
- The EOS S3 SoC platform enables advanced sensor processing applications for smartphone, wearables & IoT applications with substantially lower power consumption than traditional MCU solutions
- Initial tier-one customer shipments are scheduled for late June
QuickLogic Corporation (
The EOS S3 sensor processing platform is a multi-core SoC that enables a vast array of concurrent sensor applications, from basic to computationally demanding algorithms for smartphone, wearable, and Internet of Things (IoT) devices. Unlike traditional MCU-based solutions, the EOS S3 sensor processing platform enables sophisticated algorithm partitioning to facilitate the lowest possible power consumption for a designated task.
Advanced sensor algorithms such as voice triggering, motion compensated heart rate monitoring, and indoor navigation can be implemented at significantly lower levels of power consumption than competing MCU-based solutions. Low power consumption enables OEMs to dramatically extend battery life for advanced applications, and with that, significantly enhance the user experience.
"The EOS S3 employs always-on, context-aware sensing capabilities while staying well within the strict power budgets of smartphone, wearable, and IoT designs," said Brian Faith, vice president of worldwide marketing at QuickLogic Corporation. "Now that this leading edge platform has been production qualified, the top-tier OEMs we've been working with know that they can reliably scale up their manufacturing to high-volume production levels."
Key Features
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Feature Details
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Processor Cores - 578 KB of aggregate SRAM for code and
data storage
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QuickLogic Proprietary
microDSP Flexible Fusion
Engine - 50 KB SRAM for code
- 16 KB SRAM for data
- Very Long Instruction Word (VLIW)
microDSP architecture
- 30 microWatts/MHz
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ARM Cortex M4F - Up to 80 MHz
- Up to 512 KB SRAM
- 32-Bit, includes Floating Point Unit
- 75 microWatts/MHz
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Programmable Logic - 2,800 Effective logic cells
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Integrated Voice - Always-On Voice Trigger and Integrated
Phrase Recognition Capability, based on
Sensory TrulyHandsFree® technology
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- Integrated I2S and PDM microphone input
with support for mono and stereo
configurations
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- Integrated PDM to PCM conversion
- Integrated Sensory Low Power Sound
Detector (LPSD)
- Optional PDM bypass mode to directly
drive application processor or CODEC
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Interface Support
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To Host - Integrated SPI Slave
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To Sensors and Peripherals - Integrated SPI Master (2X), I2C, UART
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To Microphones - Integrated PDM and I2S
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Additional Components
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ADC - Integrated 12-Bit Sigma Delta
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Regulator - Integrated Low Drop Out (LDO), with 1.8
to 3.6 V input support
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System Clock - Integrated 32 kHz and High Speed
Oscillator
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Package Configurations
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Ball Grid Array (BGA) - 3.5 x 3.5 mm x 0.7 mm, 0.40 mm ball
pitch,
- 64-ball, 46 user I/O's
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Wafer Level Chip Scale Package- 2.7 x 2.4 mm x 0.6 mm, 0.35 mm ball
(WLCSP) pitch,
- 42-ball, 27 user I/O's
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Development Environment - Industry Standard, IAR and Eclipse IDE
Plugin
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Software Support - Supports Android Lollipop and
Marshmallow operating systems
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