Additional talks feature technical trainings exploring system design challenges for memory and serial links along with first public demonstration of the R+ 16G Serial Link PHY

SUNNYVALE, Calif. — (BUSINESS WIRE) — January 19, 2016 — Rambus Inc. (NASDAQ: RMBS)

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Join Rambus at DesignCon for the first public demonstration of its R+ 16G Serial Link PHY along with other memory IP core solutions and tools for server, mobile and networking applications. R+ solutions combine innovative technologies and design techniques to offer advanced feature sets and improved functionality while maintaining compatibility with industry standards. Rambus executives and leading engineers will discuss advancements in the design and characterization of high-speed memory and serial link interfaces as well as cryptography and data security for chip architectures.

Rambus Speaking Engagements:

Title: Keynote: Silicon Foundations for Security
Date: Thursday, January 21, 2016
Time: 12:00 pm - 12:45 pm
Topic: The security capabilities and limitations of chips play a critical role in security. Unfortunately, these foundations typically assume complex software will be bug-free. As a result, security failures are increasingly common in today's complex and inter-connected products. Paul Kocher, founder of Cryptography Research, will explore intersections of cryptography and data security with chip architectures. Power analysis attacks will be used as an example of how layers of abstraction can conceal security challenges. The talk will also explore architectures aimed at scaling more securely, including on-chip hardware security solutions for SoCs and infrastructure needs for the manufacturing and management of complex connected devices.
Speaker: Paul Kocher, Chief Scientist, Cryptography Research Division of Rambus Inc.

Title: Analysis, Modeling and Characterization of Multi-Protocol High-Speed Serial Links
Date: Wednesday, January 20, 2016
Time: 9:20 am - 10:00 am
Topic: Improved analysis, modeling, characterization and correlation methods of multi-protocol high-speed transceivers that utilize T-coil to enhance the transmitter and receiver bandwidth, transmitter FIR filters and receiver CTLE and DFE equalizers will be presented. The key circuit blocks are measured and modeled using IBIS-AMI models and the overall system performance including the eye diagrams, BER curves are well correlated to on-die measurements. The paper will also discuss the procedure taken to model, measure and verify the high-speed transceivers to meet the standard specifications such as return loss, jitter tolerance, BER and convergence of the adaptation equalizers and CDR to optimize the margins for various channels.