The addition of SystemC is a natural extension of the OneSpin 360 DV tool suite, allowing engineers to receive the full benefits of formal Assertion-Based Verification (ABV) and automated design inspection solutions for their SystemC design code. Both C language assertions as well as the SystemVerilog Assertion (SVA) standard are supported to allow established definitions for assertion specification. The OneSpin formal debug environment and full complement of advanced formal proof engines operate seamlessly on the SystemC code.
The product line allows for both the automated design analysis capability of OneSpin 360-DV Inspect and the full assertion-based flow of OneSpin 360-DV Verify to be applied to SystemC code. The SystemC style often leveraged as an input to High Level Synthesis (HLS) tools is specifically targeted. This allows for effective functional verification to be applied directly to this design representation, rather than indirectly to the synthesis output as with previous methodologies.
"Design and verification teams are looking more closely at SystemC to meet a variety of complex electronic design requirements and need reliable assertion-based checking for rigorous verification," remarks Dr. Raik Brinkmann, OneSpin Solutions' president and chief executive officer. "Until now, there was no clear solution for the comprehensive formal verification of SystemC coded functionality. We're delighted to fill this need with OneSpin 360 DV-Verify and 360 DV-Inspect, which solves a number of challenges for SystemC language users."
Availability and Pricing
The SystemC front end, available now in a limited release version, will be included as an option to the 360 DV product line.
Pricing for the OneSpin 360 DV product line is available upon request.
OneSpin at DVCon
OneSpin 360 DV-Verify and the entire OneSpin Product Family will be demonstrated in Booth #701 during DVCon Monday, March 2, from 5-7 p.m. and Tuesday and Wednesday, March 3 and 4, from 2:30-6 p.m. at the DoubleTree Hotel in San Jose, Calif.
OneSpin Solutions organized a panel titled, "SystemC -- Forever a Niche Player Or Rising Star of Chip Design?" to be held Wednesday, March 4, at 1 p.m. in the Oak/Fir room. It will be moderated by Bryon Moyer of EE Journal. Panelists include Michael McNamara of Adapt-IP, Bill Neifert from Carbon Design Systems, Victoria Mitchell of Altera and Dr. Brinkmann.
Sven Beyer from OneSpin will present "Detecting Harmful Race Conditions in SystemC Models Using Formal Techniques" during the Formal and Semi-Formal Techniques session Wednesday, March 4, at 2:30 p.m. in the Oak room.
The DVCon website can be found at: www.dvcon.org
About OneSpin Solutions
Electronic design automation (EDA) supplier
OneSpin Solutions award-winning formal verification technology is based on more than 300 engineering years of development and application service experience. OneSpin's comprehensive product line simplifies designer verification, increases intensive block verification coverage, eliminates design refinement problems, and provides automated solutions for many complex verification problems. Leading telecommunications, automotive, consumer electronics and embedded systems companies rely on OneSpin to achieve the highest possible verification quality while reducing their time-to-market pressures. Its United States headquarters is located in San Jose, Calif. Corporate headquarters is in Munich, Germany. Email:
info@onespin-solutions.com. Website:
www.onespin-solutions.com.
OneSpin, OneSpin Solutions, OneSpin 360, the OneSpin logo and Quantify are trademarks of OneSpin Solutions GmbH. All other trademarks are the property of their respective owners.
For more information, contact: Nanette Collins Public Relations for OneSpin Solutions (617) 437-1822 Email Contact
