NEWS: Woodcliff Lake, NJ and Chester Springs, PA — Jan 28, 2015 — Intellectual property provider CAST, Inc. is making secure, efficient, hardware-based data compression easier for designers to build into systems by adding data compression cores sourced from new partner Sandgate Technologies to its line of processors, peripherals, and other semiconductor IP.

The ZipAccel-C Compression and ZipAccel-D Decompression IP Cores are hardware lossless compression engines that comply with the popular Deflate/Inflate, GZIP/GUNZIP, and ZLIB compression standards. Configurable options (including encryption) help designers optimize feature, performance, and area trade-offs for each particular system.

The cores deliver what CAST believes are the best performance figures in the industry, enabling:

• Single threaded data throughput in excess of 100Gbps even in low-cost FPGAs, exceeding that of acceleration boards and ASSPs currently in the market;
• Hardware compression efficiency that matches the highest degree of compression possible in software (i.e., Unix/Linux “gzip -9”); and
• Compression latency lower than 15 clock cycles, making feasible the use of compression for the memory interfaces within SoCs.

“The engineers at Sandgate Technologies are among the world’s most experienced in designing and delivering hardware data compression, and we are proud to establish this new partnership with them,” said Nikos Zervas, chief operating officer for CAST. “These fast, full-featured, resource-saving compression cores are perfect for offloading processors, cutting memory size and cost, speeding wireless or networked communication, and other critical factors in both traditional and new applications.”

“We have worked to perfect hardware compression technology over many years and through multiple customer iterations, and are very proud of the state-of-the-art versions we’re shipping today,” said Chad Spackman, chief executive officer for Sandgate Technologies. “We’re very excited to begin this new partnership with CAST, and through them to help more customers solve difficult product challenges by optimizing and deploying efficient data compression.”

Capable, Configurable Hardware Compression and Decompression

The ZipAccel compression cores support the latest applicable standards: GZIP/GUNZIP (RFC-1952), Inflate/Deflate (RFC-1951), and ZLIB (RFC-1950). They work in standalone fashion independent of a CPU, and so can offload compression and encryption responsibilities from a system processor. The compressor produces files with the compressed data payload properly encapsulated, so no post-processing is required.

Memory blocks can optionally support Error Correction Codes (ECC) to help satisfy Enterprise Class data integrity requirements, and users can tune inter-file latency to meet stringent Quality of Service (QoS) objectives. Choices of streaming data and bus interfaces help simplify system integration.

Encryption is handled through optional integration with AES-XTS and AES-GCM IP cores. The delivered compression/encryption subsystem remains easy to integrate and use, with excellent performance and latency characteristics.

An included software model helps designers analyze processing speed and resource utilization versus compression efficiency to achieve the best combination of options and feature settings for their particular application. Support from Sandgate’s experienced team of compression engineers is also available to help customers optimize their systems.

Superior Solutions for Many Applications

Their excellent performance, easy configurability, and optional encryption make the ZipAccel cores suitable for a wide variety of applications.

SoCs integrating ZipAccel cores can readily out-perform software compression or stand-alone hardware compression units used for conventional applications like off-system storage or data communication. Internet of Things (IoT), wearables, and similar devices benefit when data compression reduces the time their energy-hungry radio frequency (RF) transmitters must operate.

ZipAccel’s exceptionally low latency and silicon usage also make possible new applications not previously feasible. For example, compression within an SoC to reduce the bandwidth and size of its central DDR memory yields savings in both memory bandwidth and energy consumption.