AUSTIN, Texas — (BUSINESS WIRE) — January 22, 2014 — The Silicon Integration Initiative (Si2) has announced several technology donations and contributed work which will facilitate the development of open PCells (parameterized cells) standards for IC design. These contributions will be presented at a Workshop on PCell Standards Development to be held on January 29, 2014, 1PM – 5PM, at the Network Meeting Center-Techmart in Santa Clara, CA.

The use of PCells in IC designs, while necessary and valuable, can cause several design interoperability issues which ultimately result in increased cost, schedule delays, and testing problems. These issues are particularly acute when developing and reusing designs incorporating PCells from multiple sources in differing formats. Si2 members have been working, under their Open PCell effort, to develop a new standard that will address these concerns. The recent technical donations from industry leaders will greatly accelerate this effort.

The Open PCell Working Group within Si2’s OpenPDK coalition is tasked to create a standard Open PCell representation that can be translated into a variety of formats used by different EDA tools. The Open PCell data is defined in XML and the functions for creating the contents of the open PCell are written in the Open PCell language. The Open PCell language is also used to define the callback functions that are run when a PCell parameter is changed and the PCell must be re-evaluated.

Developing a PCell design just once, for use on many EDA tools that includes proprietary PCell formats, is the primary goal, and several recent contributions support this paradigm and will accelerate this effort. Synopsys recently contributed a set of Application Programming Interfaces (APIs) for open PCell creation, IBM has contributed a PCell template example, and Intel is prototyping a meta-language translator that will take the Open PCell source and generate multiple target language outputs.

A key part of the Synopsys contribution is a Python API, which provides a large number of classes and methods specialized for generating PCell layouts. The Synopsys-donated Python API reduces PCell code size and complexity by providing powerful high-level abstractions for creating layout geometries.

IBM has contributed an example PCell MOS transistor template which will be used to test the design environment and inaugurates an extensive regression suite of PCell permutations and variations.

“Intel has contributed a translator that converts an OpenPCell description from the Common Language Grammar (a subset of Python) into several target languages”, says Ramond Rodriguez, Manager, EDA Supplier Management, Intel. “A significant advantage of this translation approach is that the OpenPCell source code is written once but can be used in many different design environments. The Intel translator can compile OpenPCell source code into industry standard scripting languages like Python, Tcl, and Ruby as well as proprietary scripting languages.”

At the upcoming Open PCell Standards workshop, industry experts will first describe the capabilities provided by the recent technology contributions and then solicit, from attendees, the range of additional capabilities desired for the emerging standard. New capabilities, which are determined to be valuable by the Open PCell working group, will be added to the requirements document for developing the new standard. These aligned requirements will directly drive the working group’s development and the release targets for 2014. Ultimately, Si2 targets the Open PCell standard for release before the end of 2014.

Si2 is inviting its members as well as other interested industry experts to participate. Workshop attendees should be experienced PCell developers, QA engineers, or design managers/directors that develop or fund the development of PDKs and PCells.

Registration is free of charge and is open to all interested parties. The abstract and registration information is located here: http://www.si2.org/?page=1728

About Si2

Si2 is the largest organization of industry-leading semiconductor, systems, EDA and manufacturing companies focused on the development and adoption of standards to improve the way integrated circuits are designed and manufactured in order to speed time-to market, reduce costs, and meet the challenges of sub-micron design. Now in its 26th year, Si2 is uniquely positioned to enable timely collaboration through dedicated staff and a strong implementation focus driven by its member companies. Si2 represents over 100 companies involved in all parts of the silicon supply chain throughout the world. See www.si2.org.

Silicon Integration Initiative
William Bayer, 512-342-2244, ext. 304