SAN JOSE, CA -- (Marketwired) -- Oct 22, 2013 -- Top technology experts from Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, will be presenting technologies and solutions for ARM-based designs throughout the three-day ARM TechCon 2013 conference. Come and learn more about the latest Cadence and ARM collaborations on optimized solutions, from system to silicon.

WHEN:
October 29-31, 2013

WHERE:
Santa Clara Convention Center, Booth 600
5001 Great America Parkway,
Santa Clara, CA

WHAT:
Jim Ready, chief technology advisor for Cadence will take part in a panel discussion with his peers: "The Future of Collaborative Embedded SW Development, from the Viewpoint of One Technology Chain Gang." Don't miss this exciting session, 3:30pm - 4:15pm Oct. 30, at the Expo Theater.
Other technology experts from Cadence will also be on hand to present 15 papers with ARM, customers and partners.

• Tuesday, Oct 29:
  • Maximizing Performance of ARM Cortex-A15 for Ultra-Power-Constrained Mobile Devices
    
    
  • Creating the Industry's First Cortex-A57 64-bit Processor on TSMC 16nm FinFET Process using Cadence design tools and ARM Physical IP
    
    
  • Best Practices for Physical-Aware Synthesis and Implementation on Mali T6XX GPUs

• Wednesday, Oct 30:
  • How to Measure and Optimize the System Performance of a Smartphone RTL Design (ARM & Cadence)
    
    
  • Hardware, Software, and System Debug for ARM-Based Design
    
    
  • Realizing High-Performance and Power-Efficient Implementations of ARM Cortex-A57 Processor at Advanced Process Nodes (ARM & Cadence)
    
    
  • Virtual Platform/Emulation Hybrid: High performance and RTL accuracy for system validation (NVIDIA & ARM)
    
    
  • Designing Analog-intensive Microcontroller for Internet of Things Applications
    
    
  • Get Optimal PPA for Cortex™-A12/Cortex-A57 based SoCs with Encounter RTL-to-Signoff Solutions
    
    
  • Modeling Physical Effects During Logic Synthesis to Improve Timing and Reduce Power
    
    
  • Highly Scalable Multicore ARM Cortex-A15 Verification with Specman/ e (Texas Instruments)
    
    
  • Integrating DDR PHY IP into Your ARM SoC -- Challenges and Solutions

• Thursday, Oct 31:
  • Power, Performance, and Cost-Optimized ARM Cortex-A12 Implementation in 28nm SLP (Super-Low-Power) Technology (GLOBALFOUNDRIES & Cadence)
    
    
  • Earlier Software and Hardware Co-Development Using Virtualized Board on a Emulation Platform (Broadcom & Cadence)
    
    
  • Verifying the AMBA® 4 ACE protocol - at the interface and across the interconnect (ARM & Cadence)

For a complete description of Cadence activities at ARM TechCon 2013, visit the Cadence Web site.

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available here.

© 2013 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

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